2026-10-23 スイス連邦工科大学ローザンヌ校(EPFL)

LogSync chips, measuring approximately 4×2 mm. 2026 EPFL / Lundi13 – CC-BY-SA 4.0
<関連情報>
- https://actu.epfl.ch/news/neural-chip-decodes-interactions-between-brain-r-2/
- https://ieeexplore.ieee.org/document/11685197
- https://proceedings.mlr.press/v306/liu26dt.html
- https://ieeexplore.ieee.org/document/11075022
LogSync:地域間同期抽出と適応型精神状態分類のための低消費電力対数SoC LogSync: A Low-Power Logarithmic SoC for Cross-Regional Synchrony Extraction and Adaptive Psychiatric State Classification
Daney Alex; Amitabh Yadav; Jieun Joo; Uisub Shin; Jinhan Liu; Geoffrey W. Diehl,…
IEEE Journal of Solid-State Circuits Published:09 September 2026
DOI:https://doi.org/10.1109/JSSC.2026.3728617
Abstract
Closed-loop deep brain stimulation (DBS) has emerged as a promising therapeutic approach for treatment-resistant psychiatric disorders, offering the potential to modulate pathological network activity in real time. To support such interventions, we present a 32-channel brain–computer interface (BCI) system-on-chip (SoC) that integrates two key functions: 1) adaptive, biomarker-driven classification of psychiatric states and 2) phase-locked closed-loop DBS. The SoC incorporates a 32-channel low-noise analog front-end (AFE), a logarithmic arithmetic unit (LAU) for efficient and accurate feature extraction (FE), including spectral power, phase, and connectivity biomarkers, a neural additive model (NAM) classifier with backpropagation-free online adaptation, and a programmable multi-mode stimulation controller that enables flexible coordination with an external stimulator. Fabricated in 65-nm CMOS, the chip occupies 5.46 mm2 and consumes 6.14 μ W/channel while achieving an energy efficiency of 0.197 μ J/classification. The proposed SoC was extensively validated on two intracranial electroencephalography (iEEG) datasets related to psychiatric disorders, achieving 80.9%/74.8% sensitivity and 74.2%/73.1% specificity on the multi-source interference task (MSIT) and the emotional conflict resolution (ECR) task, respectively. We further evaluated the SoC on the public DEAP dataset for electroencephalography (EEG)-based emotion recognition, achieving 70.5%/72.5% sensitivity and 69.8%/66.3% specificity for the arousal and valence states, respectively. In addition, we performed in vitro measurements and in vivo characterization in a Long-Evans rat to validate the AFE and phase-locked stimulation controller, confirming the feasibility of the proposed SoC for real-time intervention. Overall, the architecture enables accurate, low-power, and interpretable classification of complex neural states, supporting adaptive DBS for psychiatric neuromodulation and other BCI applications.
RECTOR:情動的および認知的表現学習のためのマスクされた領域チャネル時間モデリング RECTOR: Masked Region-Channel-Temporal Modeling for Affective and Cognitive Representation Learning
Jinhan Liu, Mahsa Shoaran
Proceedings of the 43rd International Conference on Machine Learning 2026
Abstract
Affective and cognitive disorders manifest as distributed, time-varying brain network dynamics across regions, channels, and time, challenging robust representation learning from EEG/sEEG for clinical diagnosis. We propose RECTOR (Masked Region–Channel–Temporal Modeling), an end-to-end self-supervised framework that unifies joint region-channel-temporal representation learning beyond fixed anatomical priors. At its core, RECTOR-SA is a hierarchical, block-sparse self-attention induced by Adaptive Functional Partitioning that evolves region structures from static anatomical definitions to adaptive functional regions. The self-supervision is driven by Masked Topology and Representation Learning, which jointly optimizes three complementary objectives: Masked Predictive Modeling, Topological Structure Modeling, and Cross-View Consistency. Across diverse benchmarks, RECTOR sets a new state-of-the-art in EEG emotion recognition and sEEG task-engagement classification. Crucially, its strong robustness to missing channels and cross-montage generalization underscores its potential for large-scale pre-training on heterogeneous EEG/sEEG, providing interpretable insights at both region and channel levels.
32チャンネル196-μW脳ネットワーク接続性抽出と適応型精神症状分類のための対数的SoC A 32-Channel 196-μW Logarithmic SoC for Brain Network Connectivity Extraction and Adaptive Psychiatric Symptom Classification
Daney Alex; Amitabh Yadav; Jieun Joo; Uisub Shin; Arshia Afzal; Jinhan Liu,…
2025 Symposium on VLSI Technology and Circuits Date Added to IEEE Xplore: 18 July 2025
DOI:https://doi.org/10.23919/VLSITechnologyandCir65189.2025.11075022
Abstract
This paper presents a 32-channel brain-computer interface SoC for closed-loop deep-brain stimulation in psychiatric disorders. The SoC integrates a 32-channel analog front-end, an efficient logarithmic feature extraction engine, a neural additive model classifier with online update, and a multimode stimulation controller. Fabricated in 65 nm CMOS, the 5.46 mm2 SoC consumes 6.14μ W/ channel, enabling accurate, low-power, and adaptive detection of psychiatric

